The present disclosure relates to dynamic element matching (DEM) circuits used for, for example, delta-sigma modulators, and specifically to techniques for reducing harmonic distortion of DEM circuits.
In general, delta-sigma modulators used in analog-to-digital (A/D) converters have higher accuracy than Nyquist A/D converters due to noise shaping techniques and oversampling techniques of the delta-sigma modulators, and thus the delta-sigma modulators are known as methods by which power consumption can be reduced. Among the delta-sigma modulators, a continuous-time delta-sigma modulator is known as a technique suitable for high-speed and broadband delta-sigma modulators. In a general continuous-time delta-sigma modulator, an input signal passes through a loop filter including a plurality of analog integrators which are cascade-connected and is then quantized by a quantizer. An output of the quantizer is fed back to a loop filter by a feedback digital-to-analog (D/A) converter as an analog signal (see, for example, Steven R. Norsworthy, Richard Schreier and Gabor C. Terms, “Delta-Sigma Data Converters Theory, Design and Simulation”, (USA), Wiley-IEEE Press, 1997, p. 1-6, H. Inose, Y. Yasuda, “A unity bit coding method by negative feedback”, (USA), Proceedings of the IEEE, November 1963, Vol. 51 p. 1524-1535).
In general, in order to improve the conversion accuracy of a delta-sigma modulator, a multi-bit quantizer has to be used. However, when a multi-bit quantizer is used, harmonic distortion occurs due to mismatch between elements of a feedback D/A converter. Therefore, in order to reduce the harmonic distortion, a dynamic element matching (DEM) circuit is used (see, for example, Y. Geerts, M. Steyaert, W. Sansen, “Design of Multi-bit Delta-Sigma A/D Converters”, (USA), Kluwer Academic Publishers, May 2002, p. 74-97).
When data weighted averaging (DWA) is used as an algorithm of a DEM circuit, new harmonic distortion occurs due to the property of the DWA, parasitic capacitance of the feedback D/A converter, and an input offset voltage of an operational amplifier in the loop filter (see, for example, Kazuo Matsukawa, and six other persons, “A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver”, Custom Integrated Circuits Conference (CICC), 2010 IEEE (USA), 19-22 Sep. 2010, p. 1-4).
FIGS. 13A and 13B are views illustrating example operation of a general DEM circuit using DWA as an algorithm. FIGS. 13A and 13B illustrate an example of a 7-bit DEM circuit.
In FIG. 13A, time (TIME) elapses downward from above, digits (CODE) on the left in the figure represent output codes of the DEM circuit, and digits (# OF CHANGES) on the right in the figure represent the number of bits whose values (“0” and “1”) have been changed between two output codes which are consecutive in time.
FIG. 13B is a view illustrating changes with time in the output codes (CODE) and changes with time in the number of bits whose values have been changed (# OF CHANGES). In FIG. 13B, the solid line represents changes with time in the output code, and the broken line represents changes with time in the number of bits whose values have been changed. In a period of time in which one cycle of change in the output code occurs, two cycles of change in the number of bits whose values have been changed occur. When a DEM circuit having such cyclicity is used in, for example, a delta-sigma modulator, second harmonics are generated due to parasitic capacitance of a D/A converter connected to the DEM circuit and an offset voltage of an operational amplifier included in a loop filter receiving an output of the D/A converter.
FIG. 14 shows an example of an output spectrum of a delta-sigma modulator when DWA is used. The thick solid line represents a digital output signal of the delta-sigma modulator after fast Fourier transform (FFT), and the thin broken line represents an output signal of a D/A converter included in the delta-sigma modulator after FFT. As illustrated in FIG. 14, second harmonics generated in the output signal of the D/A converter directly appears in the digital output signal of the delta-sigma modulator (C in FIG. 14).
To solve the problem, for example, U.S. Pat. No. 6,522,277 describes a DEM circuit in which two pointers are provided, and the two pointers are alternately moved in opposite directions, thereby reducing harmonic distortion including second harmonics.